Method of fabricating semiconductor device

ABSTRACT

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( 3 ), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and′ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide  12 , so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

This application is a Divisional application of application Ser. No.09/486,899, filed Mar. 3, 2000, which is a national stage applicationfiled under 35 USC 371 of International (PCT) Application No.PCT/JP97/03328, filed Sep. 19, 1997.

TECHNICAL FIELD

The present invention relates to the technical field of semiconductormanufacture, and, particularly, to a method of fabricating asemiconductor device that must be operated at a high speed.

BACKGROUND OF THE INVENTION

At the present time, in order to realize high speed operation of a MOStransistor constituting a MOS LSI, it has became important to decreasethe sheet resistance of the source and drain electrodes, the contactresistance of an electrode and wiring, and the parasitic capacitance ofthe source and drain.

In order to cope with the requirement, a structure, in which the sourceand drain surface is subjected at once to silicidation in aself-aligning manner, is applied particularly to a semiconductor devicethat must be operated at a high speed. In this structure, the surface ofthe electrodes is covered with a silicide having a low resistance, suchas titanium silicide (TiSi₂), cobalt silicide (CoSi₂) and the like, todecrease the sheet resistance, and the contact resistance with wiringcan also be decreased to a large extent in comparison with theconventional metal-semiconductor contact. Since the area of the sourceand drain can be reduced, the parasitic capacitance can also be reduced.Furthermore, the so-called salicide (self-aligned silicide) technique,in which, upon subjecting the surface of the source and drain tosilicidation, the upper part of a gate electrode is also simultaneouslysubjected to silicidation in a self-aligning manner, is also widelyemployed.

In the case where TiSi₂ is used, it is constituted with a metastablephase (C45 structure) having a relatively high specific resistance and astable phase (C54 structure) having a relatively low specificresistance. The conversion of the metastable phase (C45 structure) tothe stable phase (C54 structure) can be conducted by a heat treatment atabout 800° C. However, the temperature must be increased with anincrease in the fineness of the pattern. That is, it has been known thatthere is a thin line width effect, in which the phase transfer isdifficult to achieve with a fine pattern (for example, 0.2 μm or less).Therefore, in order to realize a fine pattern having a gate line widthof 0.2 μm or less, the heat treatment temperature for the phase transfermust be increased. Accordingly, the heat treatment temperature affectsthe fine source/drain diffusion layer.

A MOS LSI of recent years is constituted with a complementary MOStransistor for low electric power consumption. Therefore, it isnecessary to form a silicide layer on silicon having various dopants,such as an N⁺-type single crystal silicon region (N-type source/drain),a P⁺-type single crystal silicon region (P-type source/drain), anN⁺-type polycrystalline silicon gate electrode and a P⁺-typepolycrystalline silicon gate electrode. In the case of TiSi₂, theformation temperature thereof is greatly influenced by the dopant. Ingeneral, the thickness on the N⁺-type silicon becomes from 60 to 70% ofthat on the P⁺-type silicon. This is because Ti attracts an N-typedopant, and, as a result, the silicidation reaction is inhibited.

On the other hand, instead of TiSi₂ which has the above-mentionedproblems, CoSi₂ is being applied, since it has a small thin line effectand a small influence from the dopant.

A MOS type semiconductor device having a salicide structure, to whichCoSi₂ is applied, is disclosed, for example, in Japanese PatentLaid-Open No. 186085/1996 and Japanese Patent Laid-Open No. 274047/1996.According to these publications, the problems of increase in junctionleakage electric current and deterioration in junction withstand voltagein applying CoSi₂ and the solutions thereof are disclosed. The problemsoccur due to the following factors.

Before forming a cobalt film by sputtering, a spontaneous oxide film isformed on a surface of a diffusion layer, and when the formation of thecobalt layer and the first heat treatment are conducted under thatcondition, an interface between the diffusion layer and the CoSi filmbecomes non-uniform and uneven. An interface between the diffusion layerobtained by the second heat treatment and the CoSi₂ film cannot escapefrom the influence of the form of the interface between the diffusionlayer and the CoSi film. Furthermore, because an increase in volume isassociated with the conversion from the CoSi film to the CoSi₂ film, thedistance between the PN junction interface of the diffusion layer andthe uneven bottom surface of the CoSi₂ film becomes small. Accordingly,an increase in junction leakage electric current and deterioration injunction withstand voltage in the diffusion layer are liable to occur.

According to the technique disclosed in the former publication, afterremoving the spontaneous oxide film on the surface of the diffusionlayer by use of a hydrogen plasma in a vacuum apparatus,bis(methylcyclopentadienyl) cobalt is evaporated without breaking thevacuum, and a cobalt film is formed by a CVD method in which the gas issubjected to thermal decomposition.

According to the technique disclosed in the later publication, afterremoving the spontaneous oxide film on the surface of the diffusionlayer by use of a hydrogen plasma in a vacuum apparatus, a cobalt filmis formed by a CVD method in which an evaporated gas ofbis(hexafluoroacetylacetonato) cobalt is reduced with a hydrogen gaswithout breaking the vacuum.

The present inventors have revealed that in the case of CoSi₂, anincrease in junction leakage electric current and deterioration injunction withstand voltage occurs due to the following problems thatoccur completely separately from the problem of increase in junctionleakage electric current and deterioration in junction withstand voltagedue to the spontaneous oxide film disclosed in the publications.

As one of the measures for preventing the junction leakage between thesource/drain and the well when the source/drain is converted to CoSi₂, ashut current experimentation has been conducted. As a result, it hasbeen found that a sample having a large implantation energy to formconcentrated p+ and n+ layers to a large depth exhibit a large amount ofjunction leakage. This is a result that is completely contrary toexpectation. As a result of analysis, it has been found that thejunction leakage is ascribed to defects due to ion implantation, andthus the sample subjected to ion implantation at a high energy and ahigh dose exhibits increased junction leakage.

Therefore, in the silicidation technique on the general source and drain(an Si semiconductor region), because a silicide is formed by reacting ametallic film formed on the Si semiconductor region with Si, silicideabnormally grown to be an acicular shape and a metallic atom diffusedinto the Si semiconductor region reach the p/n junction formed under theSi semiconductor region, or silicide is abnormally grown in thehorizontal direction to reach the p/n junction at the edge part (thevicinity of the bird's beak) of the element isolation (LOCOS) region, soas to increase the junction leakage. This problem becomes severe whenCoSi₂ is selected as the silicide. The abnormal growth occurs due to ionimplantation damage, so-called residual defects, that occurs by ionimplantation in a high concentration (about 1×10²⁰ atoms/cm² or more) toa substrate for forming a source and drain, which is not recovered bythe annealing performed later.

As one of the solutions thereof, it can be considered that the filmthickness of the CoSi₂ formed on the source and drain is made thin. Inthis case, while the junction leakage can be lowered, the object ofdecreasing the sheet resistance of the source and drain cannot beachieved. Furthermore, when the film thickness of the CoSi₂ isdecreased, the CoSi₂ film is worn to the extent that it will disappearby over-etching on dry etching to form a contact hole, so as to increasethe danger of increasing the contact resistance. Accordingly, the filmthickness of the CoSi₂ on the source and drain cannot be decreasedwithout limitation.

Therefore, an object of the invention is to provide a method offabricating a semiconductor device that attains a silicide contact whilesuppressing any increase in junction leakage electric current anddeterioration in junction withstand voltage.

Another object of the invention is to provide a method of fabricating asemiconductor device having a fine wiring pattern that can be operatedat a high speed.

Furthermore, a further object of the invention is to provide a method offabricating a CMOS semiconductor device having a fine wiring patternthat can be operated at a high speed.

Still further, a more specific object of the invention is to form aCoSi₂ film on a source and drain without increasing the junction leakageof a p/n junction under the source and drain. In particular, it is anobject to form a CoSi₂ film having a sufficient thickness to decreasethe sheet residence on the source and drain without increasing thejunction leakage of a p/n junction under the source and drain.

SUMMARY OF THE INVENTION

The invention comprises a first step of implanting, into a prescribedregion of a semiconductor primary surface of a semiconductor main bodyhaving introduced thereto a first conductive type impurity, an ion of asecond conductive type, which is the reverse of the first conductivetype, to form a semiconductor region constituting a PN junction with thesemiconductor; a second step of implanting, into a surface of theprescribed region, an ion of the second conductive type impurity, toform a metal-semiconductor alloy layer to a prescribed thickness; andthen a step of forming, on a surface of the prescribed region havingbeen subjected to the second step, a metal-semiconductor alloy layerformed by reacting a metal and a semiconductor.

By conducting the ion implantation by separating the ion implantationfor forming the PN junction (the first step) from the ion implantationfor forming the metal-semiconductor alloy layer (the second step), itbecomes possible that formation of residual defects in the deep ionimplantation region near the position of the PN junction will besuppressed, and in the shallow ion implantation region at the surfaceregion, the metal-semiconductor alloy layer having a thicknesssufficient to decrease the sheet resistance is formed.

The invention also comprises a first step of implanting, into a primarysurface of a first semiconductor region of a first conductive typecomprising silicon, an ion of a second conductive type impurity, whichis the reverse of the first conductive type, to form a secondsemiconductor region constituting a PN junction with the firstsemiconductor region; a second step of implanting, into the primarysurface of the first semiconductor region, an ion of the secondconductive type impurity to a prescribed dose amount, to form a silicidelayer to a prescribed thickness; thereafter a step of forming the secondsemiconductor region by a heat treatment; a step of coating a metalliclayer over a surface of the second semiconductor region; and a step ofreacting the metallic layer with silicon of the second semiconductorregion by a heat treatment, to form a metallic silicide layer.

According to the foregoing procedures, it becomes possible thatformation of residual defects in the deep ion implantation region nearthe position of the PN junction will be suppressed, and in the shallowion implantation region at the surface region, the metallic silicidelayer having a thickness sufficient to decrease the sheet resistance isformed. Thus, the metallic silicide layer having a low resistance thatdoes not increase the PN junction leakage can be formed on the surfaceof the semiconductor region.

The invention also comprises a step of thermally oxidizing a primarysurface of a first semiconductor region of a first conductive typecomprising silicon, to form a gate insulating film; a step of patternforming a gate electrode comprising polycrystalline silicon on the gateinsulating film; a first step of implanting, into a part of the primarysurface of the first semiconductor region not having the gate electrodeformed, an ion of a second conductive type impurity; a step of forming aside wall spacer on a side wall of the gate electrode; a second step ofimplanting, into a part of the primary surface of the firstsemiconductor region not having the gate electrode and the side wallspacer formed, an ion of a second conductive type impurity, which is thereverse of the first conductive type, to form a source/drain regionconstituting a PN junction with the first semiconductor region; a thirdstep of implanting, into the primary surface of the first semiconductorregion, an ion of the second conductive type impurity to a prescribeddose amount, to form a silicide layer to a prescribed thickness;thereafter a step of forming a source/drain region by a heat treatment;a step of coating a metallic layer over a surface of the source/drainregion and a surface of the gate electrode; and a step of reacting themetallic layer with silicon on the surface of the source/drain regionand the surface of the gate electrode by a heat treatment, to form ametallic silicide layer.

According to the foregoing procedures, it becomes possible thatformation of residual defects in the deep ion implantation region nearthe position of the PN junction will be suppressed, and in the shallowion implantation region at the surface region, the metallic silicidelayer having a thickness sufficient to decrease the sheet resistance isformed. Thus, the metallic silicide layer having a low resistance thatdoes not increase the PN junction leakage can be formed simultaneouslyon the surface of the semiconductor region and the surface of the gateelectrode. Therefore, a MOS semiconductor device having a fine patternand which is suitable for high speed operation can be obtained.

The invention also relates to a method of fabricating a CMOSsemiconductor device characterized by comprising a step of forming, on aprimary surface of a semiconductor substrate, a first well of a firstconductive type and a second well of a second conductive type; a step offorming a gate insulating film on surfaces of the first well and thesecond well; a step of forming, on the gate insulating film formed onthe surface of the first well, a first gate electrode comprisingpolycrystalline silicon, and forming, on the gate insulating film formedon the surface of the second well, a second gate electrode comprisingpolycrystalline silicon; a first ion implantation step of implanting,into a part of a primary surface of the first well not having the firstgate electrode formed, an ion of a second conductive type impurity; asecond ion implantation step of implanting, into a part of a primarysurface of the second well not having the second gate electrode formed,an ion of a first conductive type impurity; a step of forming, on sidewalls of the first and second gate electrodes, a side wall spacer; athird ion implantation step of implanting, into a part of the primarysurface of the first well not having the first gate electrode and theside wall spacer formed, an ion of the second conductive type impurity,which is the reverse of the first conductive type, to form asource/drain region constituting a PN junction with the first well; afourth ion implantation step of implanting, into the primary surface ofthe first well subjected to the third ion implantation step, an ion ofthe second conductive type impurity, to form a silicide layer to aprescribed thickness; a fifth ion implantation step of implanting, intoa part of the primary surface of the second well not having the secondgate electrode and the side wall spacer formed, an ion of the firstconductive type impurity, to form a source/drain region constituting aPN junction with the second well; a sixth ion implantation step ofimplanting, into the primary surface of the second well subjected to thefifth ion implantation step, an ion of the first conductive typeimpurity, to form a silicide layer to a prescribed thickness; thereaftera step of forming, in the first and second wells, a source/drain regionby a heat treatment; a step of coating a metallic layer over a surfaceof the source/drain region in the first and second well and a surface ofthe first and second gate electrodes; and a step of reacting themetallic layer with silicon of the surface of the source/drain region inthe first and second wells and the surface of the first and second gateelectrodes by a heat treatment, to form a metallic silicide layer.

According to the foregoing procedures, it becomes possible thatformation of residual defects in the deep ion implantation region nearthe position of the PN junction in the well regions will be suppressed,and in the shallow ion implantation region at the surface region, themetallic silicide layer having a thickness sufficient to decrease thesheet resistance is formed. Thus, the metallic silicide layer having alow resistance that does not increase the PN junction leakage can beformed simultaneously on the surface of the source/drain region and thesurface of the gate electrode in the well regions. Therefore, a CMOSsemiconductor device having a fine pattern and which is suitable forhigh speed operation can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a cross sectional structure of a MOSsemiconductor device according to the invention.

FIG. 2 is a view showing a plan structure of a MOS semiconductor deviceaccording to the invention.

FIG. 3 is a cross sectional view showing a step of a production processof a CMOS semiconductor device.

FIG. 4 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 3.

FIG. 5 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 4.

FIG. 6 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 5.

FIG. 7 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 6.

FIG. 8 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 7.

FIG. 9 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 8.

FIG. 10 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 9.

FIG. 11 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 10.

FIG. 12 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 11.

FIG. 13 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 12.

FIG. 14 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 13.

FIG. 15 is a cross sectional view showing a step of a production processof a CMOS semiconductor device, subsequent to FIG. 14.

FIG. 16 is a diagram showing a profile of an impurity concentration inthe depth direction of the source/drain region formed in the example ofthe invention.

FIG. 17 is a diagram showing the reverse I-V characteristics of the p⁺/njunction formed in the example of the invention.

FIG. 18 is a diagram showing the reverse I-V characteristics of the p⁺/njunction formed under another condition for comparison with the exampleof the invention.

FIG. 19 relates to the example of the invention and is a diagram showingthe generation of p⁺/n leakage on variation of the thickness of the highconcentration layer.

FIG. 20 relates to the example of the invention and is a diagram showingthe generation of p⁺/n junction leakage on variation of the junctiondepth.

FIG. 21 relates to the example of the invention and is a diagram showingthe generation of p⁺/n junction leakage on variation of the conditionsof the activation heat treatment.

FIG. 22 is a cross sectional view showing a production process of a CMOSsemiconductor device of another embodiment of the invention.

BEST MODE FOR PRACTICING THE INVENTION

In order to describe the invention in more detail, reference will bemade to an embodiment illustrated in the attached drawings.

FIG. 1 is a cross sectional view of a MOS semiconductor device formedaccording to a specific example of the invention, and FIG. 2 is a planview of the MOS semiconductor device. The cross section as seen on theline A-A in FIG. 2 is shown in FIG. 1.

The MOS semiconductor device shown in FIG. 1 is, for example, a secondconductive type (N-type) channel MOS transistor formed on a firstconductive type (P-type) single crystal silicon (Si) substrate 1. Asshown in FIG. 1, a MOS transistor having an LDD (lightly doped drain)structure is formed in a P well sectioned by an oxide film for elementisolation (LOCOS film) 2. A source region S and a drain region D of theMOS transistor (hereinafter, these are referred to a source/drainregion) each comprises a relatively shallow N-type first region 10self-aligned with a gate electrode 5, a relatively deep N-type secondregion 8 self-aligned with a side wall spacer 7 and constituting a PNjunction with the P well 3, and an N-type third region 9 having arelatively high concentration and a medium depth that is deeper than theN-type first region 10, but shallower than the second region 8, andself-aligned with the side wall spacer 7. On a surface of thesource/drain region, a cobalt silicide film (CoSi₂ layer) 12 is formedto obtain a low resistance. As shown in FIG. 2, the CoSi₂ layer 12 isformed on the whole surface of the source/drain region (SD) sectioned bythe gate electrode 5 having the side wall spacer 7 and the LOCOS film 2.

The N-type third region 9 is provided to form the CoSi₂ layer 12 havinga high concentration and a low resistance, and most of the third region9 is converted into the CoSi₂ layer. This means that it is not necessarythat the whole of the third region 9 be completely converted into CoSi₂.On the other hand, the N-type second region 8 has a low concentrationand is formed at a deep position to constitute the PN junction with theP well 3 at a position having no relationship to the formation of theCoSi₂ layer.

The relationship among the relative depth of the N-type second region,the N-type third region and the CoSi₂ layer is an important point toaccomplish the objects of the invention, and will be described later indetail.

The gate electrode 5 comprises polycrystalline silicon containing anN-type impurity, and a CoSi₂ layer 11 is formed on the surface thereofto obtain a low resistance.

A passivation film 14 is coated on the surface of the silicon substrate,on which the N-channel MOS transistor is formed. As shown in FIG. 2, acontact hole TH1 to expose a part of the CoSi₂ layer 12 formed on thesurface of the source drain region (SD) and a contact hole TH2 to exposea part of the CoSi₂ film 11 formed on the surface of the gate electrode5 are formed in the passivation film 14. A metallic wiring Ml of alaminated layer comprising a barrier layer 15 and a tungsten layer 16 isconnected to the CoSi₂ layer 12 formed on the surface of thesource/drain region (SD) through the contact hole TH1. The metallicwiring Ml of the laminated layer comprising the barrier layer and thetungsten layer is connected to the CoSi₂ layer 12 formed on the surfaceof the gate electrode 5 through the contact hole TH2. The barrier layer(15) is formed to prevent the reaction of tungsten and silicon (in thesource/drain region and the gate electrode), and is constituted with alaminated layer comprising a lower layer of titanium (thickness: about30 nm) and a upper layer of titanium nitride (thickness: from 50 to 70nm). The thickness of the tungsten layer (16) is from 300 to 400 nm.

A production process of the CMOS semiconductor device as a specificexample of the invention will be described with reference to FIGS. 3 to11. In FIGS. 3 to 11, the left side of the figures shows the process offorming an N-channel MOS transistor (NMOS), and the right side of thefigures shows the process of forming a P-channel MOS transistor (PMOS).The NMOS and the PMOS are formed on one semiconductor substrate (siliconsubstrate).

(1) As shown in FIG. 3, a silicon wafer 1 is prepared as a semiconductorsubstrate. The silicon wafer 1 is obtained by slicing a single crystalingot produced by a Czochralski method (CZ method), and a surface of thewafer 1 has a mirror polished (100) crystal plane.

A thermal oxidation film (SiO₂ film) 101 having a thickness of about 10nm is formed on the surface of the wafer 1. Subsequently, ionimplantation for forming an N well and a P well is respectivelyconducted. The side of the NMOS forming region is covered with aphotoresist mask (not shown in the figure), and a phosphorous ion (P⁺)is implanted into the side of the PMOS forming region not having thephotoresist mask formed at a prescribed energy to a prescribed doseamount through the SiO₂ film 101. The side of the PMOS forming region isthen covered with a photoresist mask (not shown in the figure), and aboron ion (B⁺) is implanted into the side of the NMOS forming region nothaving the photoresist mask formed at a prescribed energy to aprescribed dose amount through the SiO₂ film 101.

As the semiconductor substrate (silicon wafer) 1 prepared herein, anepitaxial wafer, by which a gate oxide film having a small defectdensity is obtained, is preferably used. For example, as the epitaxialwafer, that comprising a P⁺-type Si substrate (specific resistance: from0.01 to 0.04 Ω·cm) having formed on the surface thereof a P-typeepitaxial layer having a thickness of about from 4 to 5 μm (specificresistance: about 10 Ω·cm), or that comprising a P-type Si substrate(specific resistance: about 10 Ω·cm) having on the surface thereof aP-type epitaxial layer having a thickness of about from 1 to 3 μm(specific resistance: about 10 Ω·cm) is employed. The later epitaxialwafer has an advantage of low cost because auto-doping and out-diffusionfrom the substrate are small, and the epitaxial layer is thin.

(2) As shown in FIG. 4, a silicon nitride film (Si₃N₄ film) 102 isselectively formed by using a known photolithography technique on theSiO₂ film 101 to cover the PMOS forming region and the NMOS formingregion. An oxidation film for element isolation, i.e., a so-called LOCOSfilm 2, (thickness: about 350 nm) is selectively formed by thermaloxidation of the surface of the substrate 1, on which the Si₃N₄ film 102is not formed. On forming the LOCOS film, phosphorous (P) and boron (B)subjected to ion implantation into the substrate is thermally diffused,to form an N well 3N for forming the PMOS and a P well 3P for formingthe NMOS at the prescribed depth.

(3) After removing the Si₃N₄ film 102 and the SiO₂ film 101, a gateoxide film 4 of 6 nm is formed on an active region (the PMOS formingregion and the NMOS forming region) sectioned by the LOCOS oxide film 2.A non-doped polysilicon (polycrystalline silicon) film 5 having athickness of 250 nm, for example, is then formed on the gate oxide film4. Subsequently, an impurity is introduced into the non-dopedpolysilicon film 5 to obtain a low resistance. Specifically, the NMOSforming region is covered with a photoresist mask, and a boron (B⁺) ionis selectively implanted into the polysilicon film 5, so as to obtain adoped polysilicon film 5(P) for forming the PMOS. Similarly, the PMOSforming region is covered with a photoresist mask, and a phosphorous(P⁺) ion is selectively implanted into the polysilicon film 5, so as toobtain a doped polysilicon film 5(N) for forming the NMOS.

(4) As shown in FIG. 6, the doped polysilicon films 5(P) and 5(N) areworked into a gate electrode pattern by a photo-etching process. Anoxide film 103 is then formed by oxidizing the surface of the gateelectrode, i.e., a so-called light oxidation treatment is conducted.

(5) As shown in FIG. 7, in order to form an LDD (lightly doped drain),the NMOS forming region is covered with a photoresist mask, and a BF₂ ⁺ion is implanted into the N well 3N, on which the gate electrode and theLOCOS film are not formed. The conditions for the ion implantation arean energy of 10 keV and an implantation amount of 7×10¹³ per cm².Similarly, the PMOS forming region is covered with a photoresist mask,and an As⁺ (Arsenic) ion is implanted into the P well 3P, on which thegate electrode and the LOCOS film are not formed. The conditions for theion implantation are an energy of 20 keV and an implantation amount of2×10¹⁴ per cm². Subsequently, the impurities thus implanted areactivated by a heat treatment for a short period of time (RTA: rapidthermal annealing) at 950° C. for 10 seconds, to form an N-typesource/drain region (104S and 104D) and a P-type source/drain region(105S and 105D).

(6) As shown in FIG. 8, a thermal CVD-SiO₂ film is formed on the Sisubstrate to 100 nm. The thermal CVD-SiO₂ film is then etched by ananisotropic dry etching technique to leave a side spacer 7 remaining.The side spacer 7 may comprise an SiN film instead of the thermalCVD-SiO₂ film. In the case of the SiN film, because an etching selectiveratio can be ensured with respect to the underlayer SiO₂ film coveringthe surfaces of the gate electrode, the N-type source/drain region (104Sand 104D) and the P-type source/drain region (105S and 105D), etching ofthe underlayer SiO₂ film on formation of the side spacer 7 can besuppressed.

(7) As shown in FIG. 9, a thermal CVD-SiO₂ film, as an ion implantationthrough film 17, is formed on the whole surface of the Si substrate 1 to10 nm. Subsequently, the ion implantation, which is a characteristicfeature of the invention, is conducted to form an N-channel MOSFET.

The first ion implantation (the third ion implantation step) isconducted to form a semiconductor region constituting a PN junction withthe P well. That is, the PMOS forming region is covered with aphotoresist mask PM, and ion implantation of a P⁺ ion is conducted onthe surfaces of the N-type source/drain region (104S and 104D) and thegate electrode 5N, on which the LOCOS film 2 is not formed. Theconditions for the ion implantation are, for example, an energy of 40keV and an implantation amount of 2×10¹⁴ per cm².

(8) As shown in FIG. 10, the second ion implantation (the fourth ionimplantation step) is conducted to form the N-type source/drain region(104S and 104D) and to form a silicide layer to a prescribed thicknesson the surface of the gate electrode 5N. As the impurity ion, As⁺ isapplied. The conditions for the ion implantation are, for example, anenergy of 60 keV and an implantation amount of 3×10¹⁵ per cm².

(9) As shown in FIG. 11, the ion implantation, which is a characteristicfeature of the invention, is conducted to form a P-channel MOSFET.

A first ion implantation (the fifth ion implantation step) is conductedto form a semiconductor region constituting a PN junction with the Nwell. That is, the NMOS forming region is covered with a photoresistmask PM, and ion implantation of a B⁺ ion is conducted on the surf acesof the P-type source/drain region (105S and 105D) and the gate electrode5P, on which the LOCOS film 2 is not formed. The conditions for the ionimplantation are, for example, an energy of 25 keV and an implantationamount of 1×10¹⁴ per cm².

(10) As shown in FIG. 12, a second ion implantation (the sixth ionimplantation step) is conducted to form the N-type source/drain region(105S and 105D) and to form a silicide layer to a prescribed thicknesson the surface of the gate electrode 5P. As the impurity ion, B⁺ isapplied as similar to the first ion implantation. The conditions for theion implantation are, for example, an energy of 5 kev and animplantation amount of 1×10¹⁵ per cm².

(11) As shown in FIG. 13, the impurities thus subjected to ionimplantation by the two separate steps for forming the N-channel MOS FETand the PN-channel MOS FET are activated by a heat treatment for a shortperiod of time (RTA) at 950° C. for 10 seconds, so as to form thesource/drain regions (106S, 106D, 107S and 107D). The depth of junctionis 180 nm in the N-type source/drain region, and 250 nm in the P-typesource/drain region. That in the shallow ion implantation layer (N+, P+high concentration layer) is about 40 nm.

In accordance with the invention, the first ion implantation in thesteps (7) and (9) forms a low concentration layer (a low concentrationregion) forming a deep PN junction, and the second ion implantation inthe steps (8) and (10) forms a shallow high concentration layer (a highconcentration region) becoming an underlayer for forming a silicidelayer of a low resistance.

The conditions for the ion implantation for forming the LDD conducted inthe step (5) are lighter than the second ion implantation for formingthe source/drain region and are set in such a manner that the doseamount is 1/10 or less.

(12) As shown in FIG. 14, the thermal CVD-SiO₂ film 17 as a through filmfor ion implantation is removed by wet etching, to expose the surface ofthe gate electrodes (5N and 5P) and the surface of the source/drainregions (106S, 106D, 107S and 107D).

(13) Subsequently, on the primary surface of the Si substrate 1, a Cofilm is formed to 10 nm, and then a TiN film is formed to 10 nm, by a DCmagnetron sputtering method. The TiN film is formed to prevent oxidationof the surface of the Co film. As shown in FIG. 12, a heat treatment isconducted in a nitrogen atmosphere at 550° C. for 30 seconds, toselectively form a cobalt silicide layer only on the source/drain regionand the gate electrode in contact with Co. The cobalt silicide in thisstep has a composition of Co/Si=1/x (x≦1). After removing the unreactedCo film and TiN film by wet etching, a heat treatment (RTA) is conductedin a nitrogen atmosphere at 750° C. for 30 seconds, to convert thecobalt silicide layer to a compound having a constant ratio of Co/Si=½(CoSi₂).

In accordance with the invention, because of the salicide process, inwhich the surface of the gate electrode is simultaneously converted intoa silicide, a cobalt silicide layer 11 formed on the surface of thegate, electrode and a cobalt silicide layer 12 formed by consuming Si(substrate) on the surface of the source/drain region are present. Thethickness of the cobalt silicide layer (12) finally becomes 30 nm. TheCoSi₂ film has a sheet resistance of 8.5Ω per square, and a specificresistance of 25 μΩ·cm. A sheet resistance of 10Ω per square is demandedfor the diffusion layer (source/drain region) in a logic LSI, and thevalue sufficiently satisfies the demand.

The steps of formation of a passivation film and formation of wiringsubsequent to the steps of forming the cobalt, silicide layer will bedescribed with reference to FIG. 1.

(14) A passivation film 14 is coated on the Si substrate. Specifically,the passivation film 14 comprises a plasma CVD film or a plasma TEOSfilm. Alternately, it comprises a laminated layer comprising a PSG filmfor gettering of an impurity and the plasma process films describedabove.

Subsequently, in the passivation film 14, a contact hole TH1 forexposing a part of the CoSi₄ layer 12 formed on the surface of thesource/drain region (SD) and a contact hole TH2 for exposing a part ofthe CoSi₂ layer 11 formed on the surface of the gate electrode 5 arerespectively formed. Subsequently, a barrier layer 15 and a tungstenlayer 16 are formed. The laminated film is patterned by a knownphotolithography technique to form a metallic wiring Ml of the laminatedlayer.

According to the procedures described in the, foregoing, a CMOSsemiconductor device as one embodiment of the invention can be obtained.

FIG. 16 shows a SIMS (secondary ion mass spectrometry) depth profile ofthe source/drain region formed in the example. This depth profile is adepth profile measured in the region shown by the line B-B in theP-channel MOS FET shown in FIG. 1. In order to eliminate the influenceof the CoSi₂ layer, this is a result of measurement taken after wetremoving the CoSi₂ layer. In this example, the thickness of the CoSi₂layer t is 30 nm, and in the depth profile, the B concentration alreadybecomes 1×10²⁰ atoms/cm³ or less at a depth of 60 rm. The thickness ofthe high concentration layer defined by the B concentration of 1×10²⁰atoms/cm³ or more is 27 nm, and 50% or more of the B diffusion layer isconsumed for the formation of CoSi₂. Furthermore, in this example, thep⁺/n junction depth is a position of 240 nm including 30 nm for theCoSi₂ on the surface. When the cross section of the source/drain regionis observed with a TEM (transmission electron microscope), numeralresidual defects due to the second implantation for forming thesource/drain region are observed at the position of the depth of about40 nm from the surface of the substrate. On the other hand, residualdefects due to the first ion implantation, which are considered to bepresent at a deeper position, are not observed. It is considered thatthis is because the amount of defects formed is small since the doseamount is as small as 1/10 of that of the second ion implantation, andthey are recovered by the activation heat treatment. The maximum doseamount that does not generate residual defects in the first ionimplantation is 3×10¹⁴ atoms/cm². When the first ion implantation isconducted by dividing the process into plural steps, the total doseamount of each step must be 3×10¹⁴ atoms/cm² or less.

As described in the foregoing, it is important to reduce the junctionleakage so that the generation of residual defects by the ionimplantation for forming the junction (the first ion implantation inthis example) is suppressed as much as possible.

On the contrary, it is preferred that the second ion implantation forforming the high concentration layer is conducted to as high a dose aspossible to increase residual defects generated. This is because byuniformly aggregating Co to the numeral residual defects, the abnormalgrowth of the individual CoSi₂ can be made small. Therefore, the secondion implantation must be conducted with at least a dose amount of 1×10¹⁵atoms/cm² or more. When the second ion implantation is conducted bydividing the process into plural steps, the total dose amount of eachstep must be 1×10¹⁵ atoms/cm² or more.

FIG. 17 shows the reverse I-V curve of the p⁺/n junction formed in thisexample. According to this example, the specification of the junctionleakage electric current density of 1×10⁻¹³ A/um² or less on applicationof 5 v (specification (1)) demanded by a logic LSI is satisfied. Forcomparison, a sample is formed by changing only the second ionimplantation of the fabrication method of the example to a BF₂ ⁺ ion, anenergy of 40 keV and a dose amount of 1×10¹⁵ per cm². This sample isreferred to as a “comparative example” herein for convenience. Thereverse I-V characteristics of the comparative example are measured. Thereverse I-V curve of the p⁺/n junction of the comparative example(number of samples: 3) is shown in FIG. 18. In the case of thecomparative example, the high concentration layer becomes about 65 nm tobe a thickness exceeding the scope of this example, and the lower end ofthe high concentration layer is close to the p⁺/n junction plane.Accordingly, when the applied voltage is increased, a junction leakageelectric current flows in some samples.

FIG. 19 shows generation of p⁺/n junction leakage on variation of thethickness of the high concentration layer. In the sample measured, inthe two ion implantation processes to form the source/drain region, theconditions of the first implantation of an energy of 25 keV and animplantation amount of 1×10¹⁴ are fixed, and the thickness of the highconcentration layer is varied by conducting the second implantation withvarying the energy. FIG. 19 shows the ratios of the samples that satisfythe specification (1) and the specification of the junction leakageelectric current density of 5×10⁻¹⁴ A/um² or less on application of 5 V(specification (2)), which is more severe than the specification (1). Itcan be well understood that when the thickness of the high concentrationlayer exceeds 30 nm, which is the same as the CoSi₂ layer, samples notsatisfying the specifications appear.

The case will be described where the Co film formed on the Si substrateis made thick, to make the CoSi₂ layer formed by silicidation thickerthan 30 nm. In this case, the thickness of the high concentration layermust be increased in proportion to the thickness of the CoSi₂ layer. Oneof the reasons for this is that the amount of reacting Co is increasedto make the depth of the abnormal growth Co₂Si deeper, and thus, inorder to suppress it into the high concentration layer, a thicker highconcentration layer is required. When the consuming thickness of the Sisubstrate is increased, the high concentration layer must be formed at adeeper position by increasing the energy of the second implantation forforming the high concentration layer, and it is necessary to increasethe thickness of the high concentration layer in proportion to thethickness of the CoSi₂ layer from the standpoint that when theimplantation energy is increased, the depth profile of the dopant isbroadened to make the control different in the depth direction, and thusthe scale must be enlarged as a whole.

The case will be described where the Co film formed on the Si substrateis made thin on the contrary, to make the CoSi2 layer thinner than 30nm. In this case, however, a CoSi₂ layer of at least 20 nm is necessarybecause the resistance of the CoSi₂ layer is increased to decrease theadvantage of the silicidation on the source/drain region. According tothe invention, when the CoSi₂ layer is made thin, the necessarythickness of the high concentration layer is also small as a matter ofcourse, but it is practically advantageous to use a high concentrationlayer of about 30 nm including some allowance, but not to use anexcessively thin high concentration layer. That is, there aredisadvantages of thinning the high concentration layer in that technicaldifficulty is increased since implantation with a lower energy isrequired to form the thin high concentration layer, and the allowancefor fluctuation in film thickness of the CoSi₂ layer is reduced.

FIG. 20 shows generation of p⁺/n junction leakage on variation of thejunction depth. In the sample measured in FIG. 17, contrary to thesamples in FIG. 19, in the two ion implantation process for forming thesource/drain region, the conditions of the second implantation of anenergy of 5 keV and an implantation amount of 1×10¹⁵ are fixed, and thejunction depth is varied by conducting the first implantation whilevarying the energy. FIG. 17 shows the ratios of the samples that satisfythe specification (1) and the specification (2). It is understood thatwhen the junction depth X_(j) becomes shallow to X_(j)<4xt with respectto the thickness t=30 nm of the CoSi2 layer, samples not satisfying thespecifications appear.

FIG. 21 is a diagram showing the influence of the activation heattreatment of the dopant. FIG. 21 shows the ratios of the samplessatisfying the specification (1) and the specification (2) when only theconditions of the activation heat treatment after the ion implantationfor forming the source/drain region are changed from the example.Samples not satisfying the specifications appear when the heat treatmenttemperature is 850° C., and thus a temperature of 900° C. or more isrequired for the activation heat treatment after the implantation of thesource/drain region. However, because heat diffusion of the dopantoccurs when the heat treatment is conducted at 900° C. or more to bringabout a danger of deteriorating the device characteristics, it isnecessary that the treatment time is 60 seconds or less to suppress theheat diffusion of the dopant at the minimum. That is, while theinvention is able to suppress the abnormal growth of Co₂Si becoming acause of the junction leakage due to aggregation of Co, by decreasingthe residual defects in the vicinity of the p/n junction, in the casewhere the heat diffusion due to the activation heat treatment of thedopant is considerable, the position of generation of the residualdefects and the position of the p/n junction deviate from each other,and thereby the junction leakage itself is decreased. The reason why theconcentration profile of the dopant can be defined instead of theposition and the density of the residual defects in the scope of theinvention is that substantially no heat diffusion of the dopant occurson the activation heat treatment of the dopant, and the concentrationprofile on the ion implantation is maintained as it is. Therefore, itbecomes possible to handle the high concentration region of the dopantas the region where the residual defects are generated on implantation.

FIG. 22 shows another embodiment of the invention. That is, a shallowgroove isolation layer 20 is employed instead of the LOCOS film 2 forelement isolation in the former example. In this case, in comparison tothe element isolation by the LOCOS film, there is no bird's beakproblem, and further high integration becomes possible by flattening ofthe substrate (employment of CMP).

After forming the shallow groove isolation layer 20, P and N wells areformed. As the subsequent steps, the same steps as the former examplefrom the step (3) in the former example are conducted.

Finally, the concept of the invention is summarized as follows: When anSi substrate having a Co film adhered thereto is heated, Co firstlydiffuses into the Si substrate to form a compound Co₂Si. At this time,Co diffuses into a deep position of the substrate by tracing residualdefects having a linear form remaining in the Si substrate. There is atendency that Co aggregates around the defects, and as a result, aphenomenon occurs in that Co₂Si suffers abnormal growth into the deepposition of the Si substrate at the defect part. In the case where theCo₂Si thus abnormally grown reaches the vicinity of the p/n junction,junction leakage occurs at that position. When the implantation into thesource/drain is conducted to a low concentration, i.e., the source/drainregion is made to have a low concentration, the residual defects can bedecreased to suppress the abnormal growth of Co₂Si. Accordingly, thejunction leakage ascribed to the abnormal growth can be suppressed.However, only by simply making the source/drain region have a lowconcentration, the contact resistance between source/drain region andthe CoSi₂ layer formed thereon becomes high. In order to prevent this, ahigh concentration layer is formed under the CoSi₂ layer. The highconcentration layer is formed at a shallow position by ion implantationof high concentration, and this means that the layer contains a largeamount of residual defects, into which a large amount of Co diffuses. Inorder to prevent the diffusion of Co into the deep position, thethickness of the high concentration layer is limited to the same valueor less as the CoSi₂ layer. The high concentration layer is alsoeffective to suppress the abnormal growth of Co₂Si. That is, since theresidual defects are present in the high concentration layer at a highdensity, the abnormal growth of Co₂Si frequently occurs. However,because it has numerous defects around the whole thereof, it is not thecase where only a part of Co₂Si considerably grows into the deepposition, and the growth is terminated when it uniformly grows to theshallow position. Because the p/n junction is present at the far deeperposition, the junction leakage does not occur when the abnormal growthis terminated at the shallow position. According to these mechanisms,the junction leakage is effectively suppressed.

Associated with fineness, the source/drain resistance is increased, andthe contact resistance is also increased since the contact hole becomessmall.

Therefore, in the future, the silicidation of the source/drain cannot beavoided in any LSI product.

Therefore, the invention is effective to apply to a high speed logicLSI, a high speed SRAM, a DRAM and an on-chip LSI having both memory andlogic.

1. A method of fabricating a semiconductor device, comprising steps of:(a) forming a gate electrode of an n-channel MISFET over an elementforming region of a first semiconductor region of p-type conductivityformed in a semiconductor body and a gate electrode of a p-channelMISFET over an element forming region of a second semiconductor regionof n-type conductivity formed in said semiconductor body, wherein eachof said element forming regions is defined by a shallow groove isolationlayer such that said shallow groove isolation layer is formed by a CMPmethod; (b) after said step (a), implanting ions in said firstsemiconductor region to form a third semiconductor region of n-typeconductivity; (c) after said step (a), implanting ions in said secondsemiconductor region to form a fourth semiconductor region of p-typeconductivity; (d) after said steps (b) and (c), forming side wallspacers on side surfaces of said gate electrodes; (e) after said step(d), implanting ions in a first region in said first semiconductorregion to form a fifth semiconductor region of n-type conductivity; (f)after said step (d), implanting ions in a region deeper than said firstregion in said first semiconductor region to form a sixth semiconductorregion of n-type conductivity: (g) after said step (d), implanting ionsin said second semiconductor region to form a seventh semiconductorregion of p-type conductivity; (h) after said step (d), implanting ionsin said second semiconductor region to form an eighth semiconductorregion of p-type conductivity; and (i) after said steps (e), (f), (g)and (h), forming a cobalt silicide layer in said fifth semiconductorregion and a cobalt silicide layer in said seventh semiconductor region,wherein a dose amount in said step (e) is greater than a dose amount insaid step (f) such that an impurity concentration of said fifthsemiconductor region is greater than an impurity concentration of saidsixth semiconductor region, wherein a dose amount in said step (g) isgreater than a dose amount in said step (h) such that an impurityconcentration of said seventh semiconductor region is greater than animpurity concentration of said eighth semiconductor region, wherein ajunction depth of said sixth semiconductor region is greater than ajunction depth of said fifth semiconductor region, wherein a junctiondepth of said eighth semiconductor region is greater than a junctiondepth of said seventh semiconductor region, wherein said gate electrodeof said n-channel MISFET is N-type gate electrode, and wherein said gateelectrode of said p-channel MISFET is P-type gate electrode.
 2. A methodof fabricating a semiconductor device according to claim 1, wherein saidMISFETs are included in a static random access memory (SRAM).
 3. Amethod of fabricating a semiconductor device according to claim 1,wherein said MISFETs are included in a dynamic random access memory(DRAM).
 4. A method of fabricating a semiconductor device according toclaim 1, wherein said MISFETs are included in a logic LSI.
 5. A methodof fabricating a semiconductor device according to claim 1, wherein saidMISFETs are included in an LSI having both memory and logic.
 6. A methodof fabricating a semiconductor device according to claim 1, wherein saidstep (i) includes sub-steps of: forming a cobalt film over said thirdsemiconductor region and said fourth semiconductor region; forming atitanium nitride (TiN) film over said cobalt film; and performing a heattreatment to form said cobalt silicide layers.
 7. A method offabricating a semiconductor device according to claim 1, wherein in saidstep (e), arsenic ion is implanted, and wherein in said step (f),phosphorus ion is implanted.
 8. A method of fabricating a semiconductordevice according to claim 1, wherein in said step (g), boron ion isimplanted, and wherein in said step (h), boron ion is implanted.
 9. Amethod of fabricating a semiconductor device according to claim 1,further comprising the step of: (j) after said steps (b) and (c),forming an insulating film over said third semiconductor region and saidfourth semiconductor region, wherein said steps (e), (f), (g) and (h)are conducted through said insulating film.
 10. A method of fabricatinga semiconductor device according to claim 1, wherein a junction depth ofsaid third semiconductor region is shallower than a junction depth ofsaid sixth semiconductor region, and wherein a junction depth of saidfourth semiconductor region is shallower than a junction depth of saideighth semiconductor region.
 11. A method of fabricating a semiconductordevice according to claim 1, wherein said third semiconductor region andsaid fourth semiconductor region serve as lightly doped drains (LDD).12. A method of fabricating a semiconductor device according to claim 1,wherein said fifth semiconductor region and said sixth semiconductorregion serve as source or drain regions.
 13. A method of fabricating asemiconductor device according to claim 1, wherein said seventhsemiconductor region and said eighth semiconductor region serve assource or drain regions.
 14. A method of fabricating a semiconductordevice, comprising steps of: (a) forming a gate electrode of a MISFETover an element forming region of a first semiconductor region of afirst conductivity type formed in a semiconductor body, wherein theelement forming region is defined by a shallow groove isolation layersuch that the shallow groove isolation layer is formed by a CMP method,and wherein a gate length of the gate electrode is less than 200 nm; (b)after the step (a), implanting ions in the first semiconductor region toform a second semiconductor region of a second conductivity typeopposite to the first conductivity type; (c) after the step (b), forminga side wall spacer on a side surface of the gate electrode; (d) afterthe step (c), implanting ions in a first region in the firstsemiconductor region to form a third semiconductor region of the secondconductivity type; (e) after the step (c), implanting ions in a secondregion deeper than the first region in the first semiconductor region toform a fourth semiconductor region of the second conductivity type; and(f) after the steps (d) and (e), forming a cobalt-silicide layer in thethird semiconductor region, wherein a dose amount in the step (d) isgreater than a dose amount in the step (e) such that an impurityconcentration of the third semiconductor region is greater than animpurity concentration of the fourth semiconductor region.
 15. A methodof fabricating a semiconductor device according to claim 14, wherein theMISFET is included in a static random access memory (SRAM).
 16. A methodof fabricating a semiconductor device according to claim 14, wherein theMISFET is included in a dynamic random access memory (DRAM).
 17. Amethod of fabricating a semiconductor device, comprising steps of: (a)forming a gate electrode of a MISFET over an element forming region of afirst semiconductor region of a first conductivity type formed in asemiconductor body, wherein the element forming region is defined by ashallow groove isolation layer such that the shallow groove isolationlayer is formed by a CMP method; (b) after the step (a), implanting ionsin the first semiconductor region to form a second semiconductor regionof a second conductivity type opposite to the first conductivity type;(c) after the step (b), forming a side wall spacer on a side surface ofthe gate electrode; (d) after the step (c), implanting ions in a firstregion in the first semiconductor region to form a third semiconductorregion of the second conductivity type; (e) after the step (c),implanting ions in a second region deeper than the first region in thefirst semiconductor region to form a fourth semiconductor region of thesecond conductivity type; and (f) after the steps (d) and (e), forming acobalt-silicide layer in the third semiconductor region, wherein a doseamount in the step (d) is greater than a dose amount in the step (e)such that an impurity concentration of the third semiconductor region isgreater than an impurity concentration of the fourth semiconductorregion.
 18. A method of fabricating a semiconductor device according toclaim 17, wherein the MISFET is included in a static random accessmemory (SRAM).
 19. A method of fabricating a semiconductor deviceaccording to claim 17, wherein the MISFET is included in a dynamicrandom access memory (DRAM).
 20. A method of fabricating a semiconductordevice, comprising steps of: (a) forming a gate electrode of ann-channel MISFET over an element isolation region of a firstsemiconductor region of p-type conductivity formed in a semiconductorbody, and a gate electrode of a p-channel MISFET over a main surface ofa second semiconductor region of n-type conductivity formed in saidsemiconductor body, wherein the element forming region is defined by ashallow groove isolation layer such that the shallow groove isolationlayer is formed by a CMP method, and wherein a gate length of each ofsaid gate electrodes is less than 200 nm; (b) after said step (a),implanting ions in said first semiconductor region to form a thirdsemiconductor region of n-type conductivity; (c) after said step (b),forming side wall spacers on side surfaces of said gate electrodes; (d)after said step (c), implanting ions in a first region in said firstsemiconductor region to form a fourth semiconductor region of n-typeconductivity; (e) after said step (c), implanting ions in a secondregion deeper than said first region in said first semiconductor regionto form a fifth semiconductor region of n-type conductivity; and (f)after said steps (d) and (e), forming a cobalt-silicide layer in saidfourth semiconductor region, wherein a dose amount in said step (d) isgreater than a dose amount in said step (e) such that an impurityconcentration of said fourth semiconductor region is greater than animpurity concentration of said fifth semiconductor region, wherein saidgate electrode of said n-channel MISFET is an N-type gate electrode, andwherein said gate electrode of said p-channel MISFET is a P-type gateelectrode.
 21. A method of fabricating a semiconductor device accordingto claim 20, wherein the MISFET is included in a static random accessmemory (SRAM).
 22. A method of fabricating a semiconductor deviceaccording to claim 20, wherein the MISFET is included in a dynamicrandom access memory (DRAM).
 23. A method of fabricating a semiconductordevice, comprising steps of: (a) forming a gate electrode of ann-channel MISFET over an element isolation region of a firstsemiconductor region of p-type conductivity formed in a semiconductorbody, and a gate electrode of a p-channel MISFET over a main surface ofa second semiconductor region of n-type conductivity formed in saidsemiconductor body; (b) after said step (a), implanting ions in saidfirst semiconductor region to form a third semiconductor region ofn-type conductivity; (c) after said step (b), forming side wall spacerson side surfaces of said gate electrodes; (d) after said step (c),implanting ions in a first region in said first semiconductor region toform a fourth semiconductor region of n-type conductivity; (e) aftersaid step (c), implanting ions in a second region deeper than said firstregion in said first semiconductor region to form a fifth semiconductorregion of n-type conductivity; and (f) after said steps (d) and (e),forming a cobalt-silicide layer in said fourth semiconductor region,wherein a dose amount in said step (d) is greater than a dose amount insaid step (e) such that an impurity concentration of said fourthsemiconductor region is greater than an impurity concentration of saidfifth semiconductor region, wherein said gate electrode of saidn-channel MISFET is an N-type gate electrode, and wherein said gateelectrode of said p-channel MISFET is a P-type gate electrode.
 24. Amethod of fabricating a semiconductor device according to claim 23,wherein the MISFET is included in a static random access memory (SRAM).25. A method of fabricating a semiconductor device according to claim23, wherein the MISFET is included in a dynamic random access memory(DRAM).